in the mood to spend two grand on a pc solely to say "I compile this thing like 0.4 seconds quicker :)"

*laughs in FPGA synthesis taking hours to days*

@RememberMe sounds interesting, iirc the algorithm used scaled exponentially, so I can imagine how long it might take.

Is it possible to parallalize this?

do a AMD build with the new 5000 series processors

@linus-torvald I'm very much thinking about going with an AMD processor.

I'm not sure about the GPU yet (gonna replace my GTX 1070), but seeing the current market with the insane prices and scalpers, I'm kinda thinking of preordering a new AMD GPU as soon as I can just so I won't have to pay 1.5 times the MSRP a month later

@LotsOfCaffeine yeah during the launch they've mentioned something about amd CPU communicating with the amd gpu *.. so yeah the new amd CPU and gpu should go together very well

*smart access memory

@linus-torvald yeah I heard that this can accelerate certain tasks fairly well

Issue is, that I don't really wanna buy a new PC in the near future, I just moved and had to buy a bunch of furniture so I don't feel like spending another 2k on a PC just yet

I actually bought a new laptop as well, which will ship in december, which has an AMD CPU, but only an integrated GPU

@LotsOfCaffeine yes but not all. And limited parallelization factor of like 4 or so. Place and route especially are killers on large FPGAs (especially once you start approaching 70+ % resource utilization), the actual synthesis step is easy.

The way around it is to launch a whole bunch of designs for compile at once on a cluster, and use the time in between to make another set of designs to compile.

@RememberMe sounds rather complex, I don't work with FPGAs myself, for now I guess

@LotsOfCaffeine nah, it's just tedious. Cluster compiling is taken care of by job management systems, you just feed it stuff to do and it'll handle everything else. We do have simulators to check functional correctness and those run in minutes to hours, but a lot of things can only be convincingly checked by placing the design on the device (eg. clock crossing errors).