Learn More
Resend Email
19
12bitfloat
4y

Found this little gem in the AMD64 reference manual:

"When PCIDs are enabled the system software can store 12-bit PCIDs in CR3 for different address spaces. Subsequently, when system software switches address spaces (**by writing the page table base pointer in CR3[62:12]**), the processor **may use TLB mappings previously stored for that address space and PCID**".

later:

"Updates to the CR3 register cause the entire TLB to be invalidated except for global pages."

So let me get this straight: PCIDs allow you to reuse TLB entries (instead of flushing the entire TLB) when writing a new address space to CR3 but writing to CR3 always flushes the entire TLB anyways

Just why 🤦‍♂️

rant

amd64

osdev

wtf
Favorite
Ranter
Comments
  • 4
    4y
    The two features are probably unrelated and the programmers never spoke to each other.

    That or the first one is a hack based on the second.
  • 0
    4y
    You should email Atmel, it's not often they have ambiguous CPU manuals /s
  • 1
    4y
    Sounds like an exception when PCIDs are enabled but yeah it's worth an e-mail.
  • 2
    4y
    @mundo03 These features are actually as related as they could be. The only reason PCIDs exist is to avoid flushing the TLB
  • 1
    4y
    @hjk101 You gotta wonder how this obvious mistake can be in the offical AMD64 manual for years and years though
  • 2
    4y
    @12bitfloat then they had sone lazy fuckers over there
  • 1
    4y
    @12bitfloat yeah, why did it take you so long to figure out? 🧐
Related Rants
devRant © 2021 Hexical Labs LLC
Privacy Policy  |  Terms of Service
Add Comment