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ARM is panicking because of RISC-V. The available chips match the M0 in terms of performance, but not M3/4/7. Guess why ARM opens only M0.
Also remember that this is only the core itself. The actual work with an MCU is the peripherals. -
@molaram obviously open source probably not good for industrial project, but it’s really useful for researchers and hobbyists.
The commercial License of ARM IP Costs $40k to $75k
Also now add the cost of research, engineering , then fabrication of those design it’s just not possible for small startups.
That’s why the move to make these industry standard IP free is a novel one -
@molaram On the other hand, server Linux works well. The essential condition for that is real money with real devs, not just a hobbyist show. That in turn requires a business model that aims for commodisation of the open parts (e.g. selling server hardware).
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@molaram Since Linux has a spaghetti shitshow instead of a proper driver architecture like Windows, the kernel IS the hardware support.
And the rest, I mean server Linux works so well including its application stack that it has won in the server world. Closed source commercial alternatives didn't bring enough to the table. -
@Fast-Nop yes that’s the fun part designing custom peripheral on top of AHB Bus around cortex M0.
Think like this earlier PCB was niche thing and was expensive when open hardware community came into picture companies started to take PCB Design orders from hobbyist , diy engineers and that resulted in cool things like raspberry pi.
If you apply same to SoC design making CPU IP free is step one now i want some company to reduce costs of their 40nm node that are already optimized for M0 -
@hardfault That's not comparable because you can make PCBs economically in small sample sizes, but you can't do that with SoCs. That's rooted in the production process.
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@molaram That is unlikely because Apple doesn't care about its hardware. 68k, PPC, x86, ARM. Their garden is walled in software, and you can do that even on open hardware.
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@Fast-Nop there’s is a high failure rate in PCBs also but we have gotten better over the years. I believe when whole world will shift to 5nm or 7nm nodes (except intel , fucking peasants) it will make a logical sense for older process nodes to become more robust , (now i also want to know the oldest node process we can use for M0)
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@hardfault PCBs have a completely different production process that is basically just using some acid to remove superfluous parts of a copper layer on a piece of plastic.
Chip production, on the other hand, requires much more setup that is only viable for high quantities. That will not be addressed through shrinking the structures. That's also why just having independent chip producers will not solve this issue - obviously, since we already have e.g. TSMC and Global Foundries. -
@molaram actually back in 1980 the ARM was a joint venture between three apple computers, acron computers and vlsi technology.
Basically if you where using any arm chip back then you probably be paying apple some royalties -
@hardfault Yeah ARM originally was "Acorn RISC Machine". RISC vs. CISC still was a thing back then.
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matt-jd10095y@molaram yes I wouldn't have any issues with that, if it's aero I trust them to have properly tested the system as licensing has nothing to do with quality. There's as much shit code in proprietary code as in open source, you just can't see it, I mean just look at all the rants here related to colleagues and code bases
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matt-jd10095y@molaram yes I wouldn't have any issues with that, if it's aero I trust them to have properly tested the system as licensing has nothing to do with quality. There's as much shit code in proprietary code as in open source, you just can't see it, I mean just look at all the rants here related to colleagues and code bases
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@molaram Then again, also commercial chips do have errata sheets. Even chips used for critical stuff. That's why the SW devs read up on them, and you never have only one computer making critical decisions.
Also, testing is pretty big for such projects. In avionics, anything from DAL C upwards requires code coverage during the testing procedures, AND explaining anything not covered. That's why pulling in millions of code lines for these components isn't feasible.
You can use e.g. some Linux board in an aircraft, but only for non-essential systems. If e.g. the in-flight entertainment system crashes, that's annoying, but doesn't matter much. -
@molaram That's why you don't use anything new for critical stuff. You'd be surprised how many contemporary aircraft systems are running on 8051 CPUs. Because even for commercial chips, it takes time to discover the bugs that will be described in the errata sheets later.
"Move slowly and let others break things". -
@Fast-Nop
I agree with your prediction on RISC-v just went through the docs. Seems though it’s robustness have to be verified. Trying to download some core from Sifive . I Think this will be wild boost that chip industry needed -
@hardfault Hopefully, they don't take the Harvard thing too far - the progmem shit in AVR sucks donkeys.
Cortex-M has different busses for data and instructions, but read-only variables can be put into flash-ROM seamlessly. -
@Fast-Nop agree but I & D buses separations comes at M4 i think in M0 it’s not present, i am more interested in compact microcontroller design but one that is higher mips. I see RISC/V have micro-op fusion basically a kind of out of other execution system this paired with nice 3 stage pipeline can make a highly real-time chip.
I have never heard a microcontroller doing out of order execution before
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ZioCain5I'm pretty sure it was already posted in here, but I found it today Did you get it?
I just saw that ARM released their design start IP for Cortex M0 for free to the masses , it’s obfuscated verilog code.
I worked on SoC design based on this in college but it took a lot of paper work to get these file but now they are free to download
This is exciting as this makes a open-source community based microcontroller design possible.
Only missing piece here is the verilog compiler they use is not open source .
Has anyone messed around with Cortex M0 DS + ghdl or iverilog. I am about to start a little side project will update more on this
question
arm
design start
ip
verilog